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alcinnz

Hey @loke , do you know of prior art for exposing RAM (& an address into it) to a CPU as registers?

I'm harvesting links for comparing my "Arithmetic Core" design to 6502. I have plenty of 6502 links...

Jan 19, 2025, 05:28 AM·Public
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Elias Mårtenson

@alcinnz not really, but the opposite was common. The Apllo AGC did this for example. The registers were just addresses in memory.

Another example that took it even further was the Burroughs architecture which didn't even have registers at all. Instead it used a stack architecture.

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alcinnz

@loke Thanks, it was worth asking.

I'll look up Burroughs architecture, I believe I have a spot for such a link!

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leah & glitches & bits, oh my!

@loke @alcinnz there's the TMS9900, which didn't have internal registers as such at all - just a workspace pointer, which pointed to a 32-byte chunk of RAM that was then treated like a set of registers by the instruction set

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alcinnz

@millihertz @loke My 1st thought: That could've sped up task-switching!

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leah & glitches & bits, oh my!

@alcinnz @loke indeed it did - TI explicitly called repointing the WP a "context switch" (and implicitly drew a direct parallel between calling a subroutine and switching to a coroutine)

unfortunately as CPUs rapidly outstripped memory in speed, it would've slowed down everything else dramatically... but TI's failure to effectively market the 99xx range solved that problem for them ;-)

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